1. Field of the Invention
The present invention relates to a delay measuring device mainly for measuring a delay amount in a semiconductor device.
2. Description of the Related Art
As a semiconductor integrated circuit has an increasingly larger capacity in recent years, the variability of characteristics in one semiconductor chip is increasingly notable. As a result, it becomes increasingly necessary to accurately grasp a delay amount generated in a semiconductor chip in order to manufacture a semiconductor device having a high quality.
However, when the delay amount is measured at a plurality of positions inside the semiconductor chip according to the conventional technology, it is necessary to provide a significantly large number of wiring lines in a delay measuring device, which unfavorably increases a circuit area. In order to reduce the circuit area, it is necessary to reduce the number of the positions where the delay amount is to be measured.
Below is described a conventional delay measuring device recited in No. 2005-322860 of the Japanese Patent Applications Laid-Open. FIG. 7 is a circuit diagram illustrating a first constitution of the conventional delay measuring device. The delay measuring device comprises a two-input NAND gate 31 and an even number of inverters 32a, 32b, . . . , 32n which are cascade-connected to an output of the NAND gate 31. An output of the rearmost inverter 32n is fed back to one of the two input terminals of the NAND gate 31, and the inverters 32a, 32b, . . . , 32n constitute a ring oscillator. Due to delay characteristics of the inverters 32a, 32b, . . . , 32n, the ring oscillator outputs a clock having a frequency conformable to the variation of the delay amount.
FIG. 8 is a circuit diagram illustrating a second constitution of the conventional delay measuring device. The delay measuring device comprises a plurality of buffers 41a, 41b, . . . , 41n cascade-connected to one another, flip-flops 42a, 42b, . . . , 42n, and a decoder 43. Outputs of the buffers 41a, 41b, . . . , 41n are respectively connected to data inputs (D) of the flip-flops 42a, 42b, . . . , 42n corresponding thereto, clock terminals of the flip-flops 42a, 42b, . . . , 42n are connected to a common supply wire of a clock CK, and Q outputs of the flip-flops 42a, 42b, . . . , 42n are inputted to the decoder 43.
When a pulse Pin is inputted to the cascade-connected buffers 41a, 41b, . . . , 41n in the delay measuring device thus constituted, the pulse is transmitted sequentially from one to the other. Then, when a pulse CK′ used for measurement is inputted thereto after the elapse of a predetermined amount of time from the input of the pulse Pin, the flip-flops 42a, 42b, . . . , 42n which are connected in parallel with the buffers arranged in a line latch output signals of the buffers 41a, 41b, . . . , 41n at once. Assuming that the signals have been transmitted to the mth buffer when the signals are latched, “1” is shown in the outputs of the m number of flip-flops, while “0” is shown in the outputs of the (n−m) number of flip-flops. When these outputs are decoded by the decoder 43, outputs signals are generated, and delay amounts are accordingly determined.
In the delay measuring device shown in FIG. 7, wherein the clock in which the delay amount is reflected is outputted, however, it is necessary to numerically convert the clock using a frequency measuring device separately provided when the clock is actually used. Further, in the case where a plurality of delay measuring devices are provided in a semiconductor chip, each of the delay measuring devices has to be individually wired, which possibly increases a circuit area. Further, in the case where the ring oscillator is used, a clock having a particular frequency is continuously generated during the delay measurement, which easily causes a noise impact on peripheral circuits.
In the delay measuring device shown in FIG. 8, a plurality of flip-flops are necessary for the measurement of the delay amount at one position, which unfavorably increases an area of the delay measuring device itself.